All digital phase-locked loops (ADPLLs) are preferred for frequency generation over traditional analog phase-locked loops (PLLs) to take advantage of process scaling. ADPLL architectures offer area savings by eliminating large loop filters, reconfigurability of the loop gain and bandwidth, and are mostly portable across processes. However, ADPLL performance inherently suffers due to time-to-digital conversion (TDC) and digital controlled oscillator (DCO) quantization errors which contribute to the in-band and out-of-band phase noise. Moreover, most ADPLLs use digital-to-analog converters (DACs) and delta-sigma (ΔΣ) modulators (or DSMs) to improve the DCO resolution, which require carefully matched custom design.